Ti-Shen (Andy) Chueh

I am a 1st year M.S. Electrical Engineering student at USC.

Recently, I am actively seeking for Hardware Engineering Internship.

I have done several projects on digital logic design and layout designs.

My professional skills are VLSI Circuit and Computer Systems Architecture.




         


USC M.S. EE
Graduate Student
2021 - 2022

ESS Research
Research Assistant
2018 - 2019

NTHU B.S. ESS
Undergraduate Student
2016 - 2019



512-bit SRAM Array Design
Date: Sept. 24, 2021

Ti-Shen Chueh
Project
12-bit Multiply-Accumulator (MAC) Unit
Date: May 12, 2021

Ti-Shen Chueh
Project
6x6 bits Multiplication (Wallace Tree Multiplier) /
16-bit Adder (Ripple Carry Adder)
Date: Apr. 13, 2021

Ti-Shen Chueh
Project
N+/P Hybrid Poly-Si Shell Structure Junctionless
Field-Effect Transistors
Date: Jul. 7, 2018

Ti-Shen Chueh, Chao-Yu Ho
Advisor: Prof. Yung-Chun Wu
Research

Template from Jon Barron and Shao-Hua Sun